4-mbit (512k x 8) mobl ? static ram cy62148dv30 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05341 rev. *d revised january 25, 2007 features ? temperature ranges ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? very high speed: 55 ns ? wide voltage range: 2.20v ? 3.60v ? pin-compatible with cy62148cv25, cy62148cv30 and cy62148cv33 ? ultra low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 8 ma @ f = f max (55-ns speed) ? ultra low standby power ? easy memory expansion with ce , and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? available in pb-free and non pb-free 36-ball vfbga, pb-free 32-pin tsopii and 32-pin soic packages functional description [1] the cy62148dv30 is a high-perf ormance cmos static ram organized as 512k words by 8 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption. the device can be put into standby mode reducing power consumption when deselected ( ce high).the eight input and output pins (io 0 through io 7 ) are placed in a high-impedance state when: ? deselected ( ce high) ? outputs are disabled ( oe high) ? when the write operation is active( ce low and we low) write to the device by taking chip enable ( ce ) and write enable ( we ) inputs low. data on the eight io pins (io 0 through io 7 ) is then written into t he location specified on the address pins (a 0 through a 18 ). read from the device by taking chip enable ( ce ) and output enable ( oe ) low while forcing write enable ( we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the io pins. logic block diagram a 1 column decoder row decoder sense amps data in drivers power down we oe io 0 io 1 io 2 io 3 512k x 8 array io 7 io 6 io 5 io 4 a 0 a 13 ce a 14 a 15 a 16 a 17 a 18 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 note: 1. for best practice recommendations, refer to the cypress application note ? system design guidelines ? on http://www.cypress.com. [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 2 of 10 pin configuration [2, 3] 36-ball vfbga pinout 32-pin soic / tsop ii pinout product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [4] max typ [4] max typ [4] max typ [4] max cy62148dv30l industrial 2.2 3.0 3.6 55 1.5 3 8 15 2 12 cy62148dv30ll industrial 55 1.5 3 8 10 2 8 cy62148dv30ll industrial 70 1.5 3 8 10 2 8 cy62148dv30ll automotive-a 70 1.5 3 8 10 2 8 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 v cc a 3 a 2 a 1 a 17 a 16 oe a 6 a 14 ce io 2 io 0 io 1 a 12 a 7 21 22 19 20 io 7 27 28 25 26 17 18 23 24 v ss a 5 a 4 io 6 io 5 io 4 io 3 a 10 a 18 a 11 a 0 a 9 a 8 a 13 a 15 top view top view a 15 v cc a 13 a 12 a 5 nc we a 7 io 4 io 5 a 4 io 6 io 7 v ss a 11 a 10 a 1 v ss io 0 a 2 a 8 a 6 a 3 a 0 v cc io 1 io 2 io 3 a 17 a 18 a 16 ce oe a 9 a 14 d e b a c f g h dnu notes: 2. nc pins are not connected on the die. 3. dnu pins have to be left floating or tied to vss to ensure proper application. 4. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 3 of 10 maximum ratings (exceeding maximum ratings may im pair the useful life of the device. for user guidelines, not tested.) storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. ............ .......... 55c to +125c supply voltage to ground potential ....................... .................. ?0.3v to v cc(max) + 0.3v dc voltage applied to outputs in high-z state [5, 6] ......................... ?0.3v to v cc(max) + 0.3v dc input voltage [5, 6] ..................... ?0.3v to v cc(max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range product range ambient temperature v cc [7] cy62148dv30l industrial ?40c to +85c 2.2v to 3.6v cy62148dv30ll cy62148dv30ll automotive-a ?40c to +85c electrical characteristics over the operating range parameter description test conditions 55 ns 70 ns unit min typ [4] max min typ [4] max v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 2.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 0.4 v i ol = 2.1 ma v cc = 2.70v 0.4 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ind?l l 8 15 ma ind?l ll 8 10 8 10 ma auto-a ll 8 10 ma f = 1 mhz ind?l l 1.5 3 ma ind?l ll 1.5 3 1.5 3 ma auto-a ll 1.5 3 ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ?0.2v, v in < 0.2v) f = f max (address and data only), f = 0 ( oe , and we ), v cc =3.60v ind?l l 2 12 a ind?l ll 2 8 2 8 auto-a ll 2 8 i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v ind?l l 2 12 a ind?l ll 2 8 2 8 auto-a ll 2 8 notes: 5. v il(min) = ?2.0v for pulse durations less than 20 ns. 6. v ih(max) = v cc +0.75v for pulse durations less than 20 ns. 7. full device ac operation assumes a 100 s ramp time from 0 to v cc(min) and 200 s wait time after v cc stabilization. [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 4 of 10 capacitance (for all packages) [8] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter description test conditions vfbga tsop ii soic unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 72 75.13 55 c/w jc thermal resistance (junction to case) 8.86 8.95 22 c/w ac test loads and waveforms parameters 2.5v (2.2v ? 2.7v) 3.0v (2.7v ? 3.6v) unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [4] max unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc = 1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v ind?l l 9 a ind?l/auto-a ll 6 a t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns data retention waveform v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns 1.5v 1.5v t cdr v dr > 1.5 v data retention mode t r ce v cc notes: 8. tested initially and after any design or process changes that may affect these parameters. 9. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 5 of 10 switching characteristics (over the operating range) [10] parameter description 55 ns 70 ns unit min max min max read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [11] 5 5 ns t hzoe oe high to high z [11,12] 20 25 ns t lzce ce low to low z [11] 10 10 ns t hzce ce high to high z [11, 12] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-up 55 70 ns write cycle [13] t wc write cycle time 55 70 ns t sce ce low to write end 40 45 ns t aw address set-up to write end 40 45 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 45 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [11, 12] 20 25 ns t lzwe we high to low z [11] 10 10 ns switching waveforms read cycle no. 1 (address transition controlled) [14, 15] address data out previous data valid data valid t rc t aa t oha notes: 10. test conditions for all parameters other than three-state parame ters assume signal transition ti me of 3 ns or less (1 v/ns), timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 . 11. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 12. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 13. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and ho ld timing should be referenced to the edge of the signal that terminates the write. 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 6 of 10 read cycle no. 2 ( oe controlled) [15, 16] write cycle no. 1 ( we controlled) [17, 18] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high data out oe ce v cc supply current address t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid t sce data io address ce we oe note 19 notes: 16. address valid prior to or coincident with ce transition low. 17. data io is high impedance if oe = v ih . 18. if ce goes high simultaneously with we high, the output remains in high-impedance state. 19. during this period, the ios are in output state and input signals should not be applied. [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 7 of 10 write cycle no. 2 ( ce controlled) [17, 18] write cycle no. 3 ( we controlled, oe low) [18] truth table ce we oe inputs/outputs mode power h x x high z deselect/power-down standby (i sb ) l h l data out (io 0 -io 7 ) read active (i cc ) l h h high z output disabled active (icc) l l x data in (io 0 -io 7 ) write active (icc) switching waveforms (continued) t wc data in valid t aw t sa t pwe t ha t hd t sd t sce ce address we data io oe t hd t sd t lzwe t sa t ha t aw t wc t hzwe data in valid t pwe t sce data io address ce we note 19 [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 8 of 10 ordering information speed (ns) ordering code package diagram package type operating range 55 cy62148dv30ll-55bvi 51-85149 36-ball vfbga (6 8 1 mm) industrial cy62148dv30ll-55bvxi 36-ball vfbga (6 8 1 mm) (pb-free) cy62148dv30l-55zsxi 51-85095 32-pin tsop ii (pb-free) CY62148DV30LL-55ZSXI cy62148dv30ll-55sxi 51-85081 32-pin soic (pb-free) 70 cy62148dv30ll-70zsxi 51-85095 32-pin tsop ii (pb-free) industrial cy62148dv30ll-70zsxa 51-85095 32-pin tsop ii (pb-free) automotive-a contact your local cypress sales repres entative for availability of these parts package diagrams figure 1. 36-ball vfbga (6 x 8 x 1 mm), 51-85149 a 1 a1 corner 0.75 0.75 ?0.300.05(36x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85149-*c [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 9 of 10 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical cont rol or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and more battery life is a trademark, of cypress semicond uctor. all product and company names mentioned in this document may be t he trademarks of their respective holders. figure 2. 32-pin tsop ii, 51-85095 figure 3. 32-pin (450 mil) molded soic, 51-85081 package diagrams (continued) 51-85095-** 0.546[13.868] 0.440[11.176] 0.101[2.565] 0.050[1.270] 0.014[0.355] 0.118[2.997] 0.004[0.102] 0.047[1.193] 0.006[0.152] 0.023[0.584] 0.793[20.142] 0.450[11.430] 0.566[14.376] 0.111[2.819] 0.817[20.751] bsc. 0.020[0.508] min. max. 0.012[0.304] 0.039[0.990] 0.063[1.600] seating plane 1 16 17 32 0.004[0.102] 51-85081-*b [+] feedback [+] feedback
cy62148dv30 document #: 38-05341 rev. *d page 10 of 10 document history page document title:cy62148dv30, 4-mbit (512k x 8) mobl ? static ram document number: 38-05341 rev. ecn no. issue date orig. of change description of change ** 127480 06/17/03 hrt created new data sheet *a 131041 01/23/04 cbd changed from advance to preliminary *b 222180 see ecn aju changed from preliminary to final added 70 ns speed bin modified footnote #6 and #12 removed max value for v dr on ?data retention characteristics? table modified input and output capacitance values added pb-free ordering information removed 32-pin stsop package *c 498575 see ecn nxr added automotive-a operating range removed soic package from product offering updated ordering information table *d 729917 see ecn vkn added soic package and its related information updated ordering information table [+] feedback [+] feedback
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